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<title>ADDSUBPD—Packed Double-FP Add/Subtract </title></head>
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<h1>ADDSUBPD—Packed Double-FP Add/Subtract</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32-bit Mode</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>66 0F D0 /r</p>
<p>ADDSUBPD <em>xmm1</em>,<em> xmm2/m128</em></p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE3</td>
<td>Add/subtract double-precision floating-point values from <em>xmm2/m128</em> to <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.128.66.0F.WIG D0 /r</p>
<p>VADDSUBPD xmm1, xmm2, xmm3/m128</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Add/subtract packed double-precision floating-point values from xmm3/mem to xmm2 and stores result in xmm1.</td></tr>
<tr>
<td>
<p>VEX.NDS.256.66.0F.WIG D0 /r</p>
<p>VADDSUBPD ymm1, ymm2, ymm3/m256</p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Add / subtract packed double-precision floating-point values from ymm3/mem to ymm2 and stores result in ymm1.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (r, w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Adds odd-numbered double-precision floating-point values of the first source operand (second operand) with the corresponding double-precision floating-point values from the second source operand (third operand); stores the result in the odd-numbered values of the destination operand (first operand). Subtracts the even-numbered double-precision floating-point values from the second source operand from the corresponding double-precision floating values in the first source operand; stores the result into the even-numbered values of the destination operand.</p>
<p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>128-bit Legacy SSE version: The second source can be an XMM register or an 128-bit memory location. The desti-nation is not distinct from the first source XMM register and the upper bits (VLMAX-1:128) of the corresponding YMM register destination are unmodified. See Figure 3-3.</p>
<p>VEX.128 encoded version: the first source operand is an XMM register or 128-bit memory location. The destination operand is an XMM register. The upper bits (VLMAX-1:128) of the corresponding YMM register destination are zeroed.</p>
<p>VEX.256 encoded version: The first source operand is a YMM register. The second source operand can be a YMM register or a 256-bit memory location. The destination operand is a YMM register.</p>
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<text y="20791.7480139" x="149.9333" style="font-size:8.000300pt" lengthAdjust="spacingAndGlyphs" textLength="132.7329773">xmm1[127:64] + xmm2/m128[127:64]</text>
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<h3>Figure 3-3.  ADDSUBPD—Packed Double-FP Add/Subtract</h3>
<h2>Operation</h2>
<p><strong>ADDSUBPD (128-bit Legacy SSE version)</strong></p>
<pre>DEST[63:0] (cid:197) DEST[63:0] - SRC[63:0]
DEST[127:64] (cid:197) DEST[127:64] + SRC[127:64]
DEST[VLMAX-1:128] (Unmodified)</pre>
<p><strong>VADDSUBPD (VEX.128 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197) SRC1[63:0] - SRC2[63:0]
DEST[127:64] (cid:197) SRC1[127:64] + SRC2[127:64]
DEST[VLMAX-1:128] (cid:197) 0</pre>
<p><strong>VADDSUBPD (VEX.256 encoded version)</strong></p>
<pre>DEST[63:0] (cid:197) SRC1[63:0] - SRC2[63:0]
DEST[127:64] (cid:197) SRC1[127:64] + SRC2[127:64]
DEST[191:128] (cid:197) SRC1[191:128] - SRC2[191:128]
DEST[255:192] (cid:197) SRC1[255:192] + SRC2[255:192]</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>ADDSUBPD:</p>
<p>__m128d _mm_addsub_pd(__m128d a, __m128d b)</p>
<p>VADDSUBPD:</p>
<p>__m256d _mm256_addsub_pd (__m256d a, __m256d b)</p>
<h2>Exceptions</h2>
<p>When the source operand is a memory operand, it must be aligned on a 16-byte boundary or a general-protection exception (#GP) will be generated.</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>Overflow, Underflow, Invalid, Precision, Denormal.</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 2.</p></body></html>